Responsibility:
1. The process includes but not limited RTL package building/RTL linting/functional regression/synthesis/timing check/formal equivalence check/gate-level simulation/performance check/power check/
2. Help to run the regression and collect the report, update the status in time.
3. As a IP/Chip level release qualification engineer, who will be the last step before hardware release, thus it is with high responsibility to make sure there is no any bugs/violations through the flows.
Requirements:
1. Basic knowledge on IC design flow and design language like verilog, familiar with RTL/Gate level simulation.
2. Basic knowledge on FPGA
3. Can do some script programming for process automation
4. Strong responsibility, self motivation, and teamwork are essential.
5. Fluent English in speaking, reading and writing.
6. Work at least 4 days per week.
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